Board impedance management

ABSTRACT

A system and method are disclosed in which separate impedance compensation circuitry is allocated for an interface according to the space occupied on a printed circuit board (PCB) by the interface. Where an interface occupies two or more layers of the PCB, an impedance compensation circuit is dedicated to each layer on behalf of the interface. By dedicating impedance compensation, not just to the interface alone, but to the physical space occupied by the interface, the system and method are able to exploit multiple-layer and same-layer trace impedances, save board space and/or provide AC timings recovery.

FIELD OF THE INVENTION

[0001] This invention relates to printed circuit boards and, moreparticularly, impedance issues involving printed circuit boards.

BACKGROUND OF THE INVENTION

[0002] Printed circuit boards, known commonly as PCBS, are ubiquitous inthe electronics industry. In addition to connecting integrated circuits(ICs) and other components, the PCB also is a mechanical mountingsurface for the devices. A multi-layered PCB typically includes at leastone signal layer and reference potential layers, also known as groundand power.

[0003] The PCB consists of a laminate of a conductive material, usuallycopper, as well as an insulating dielectric substrate. The traces formedof the copper material provide signaling paths for communication betweenthe ICs, discrete components, or other circuitry mounted on the PCB.Under certain operating conditions, the traces act like transmissionlines. In particular, board designs involving high-speed signals payclose attention to the impedance of these communication paths.

[0004] Impedance is a measure of passive opposition to the flow ofcurrent along the trace. Impedance consists of resistance (to directcurrent), reactance (to alternating current), inductance andcapacitance. The length and width of each trace, its proximity to othertraces, and the number of board layers are among the many factorsaffecting trace impedance. Generally, wider traces have lowerimpedances, where other factors are equal.

[0005] An impedance mismatch is the discontinuity between the impedancesof two communicating components. When an impedance mismatch is present,reflection along the signal trace can occur. The reflected signal willadd to or subtract from the original signal being transmitted betweenthe components, causing a distortion and, possibly, a failure of thetransmission.

[0006] Generally, PCB boards are manufactured to meet certain traceimpedances, within some tolerance. Thus, where a 50-ohm PCB isspecified, plus or minus fifteen percent, the impedance of all traces onthe PCB will be between 42.5 and 57.5 ohms. A single PCB cansimultaneously include traces of different widths, such as 50-ohm tracesand 60-ohm traces, for example. This enables signal groups withdifferent impedance requirements to simultaneously occupy the PCB. Amemory interface may have a 60-ohm impedance requirement while aprocessor interface, located on the same PCB, has a 50-ohm impedancerequirement.

[0007] Despite having a board with a known trace impedance, boarddesigners ensure that the impedance between devices matches wheneverpossible. Impedance matching ensures signal integrity by eliminatingreflections and ringing along the trace that may adversely affect systemperformance.

[0008] Most traces on the PCB are terminated, such as by addingresistors or buffers to the output and/or the input of an integratedcircuit. The output impedance or input termination of the circuit ismatched to the characteristic impedance of the connecting trace. Thisimpedance matching is a consideration for most system designs.

[0009] Many system designs include impedance compensation circuitry,such as resistive compensation or controlled impedance drivers.Impedance compensation circuitry may be dedicated to separate signalgroups of a system design. Thus, a memory controller may have its ownimpedance compensation circuitry, likewise for the processor, the I/Ocontroller, and so on. A single PCB may thus maintain several impedancecompensation circuits for various interfaces.

[0010] Studies have shown that the variation of trace impedance betweentwo locations on the same layer of the PCB is lower than when the twolocations are on different layers of the PCB. In particular, same layervariation in the trace impedance on some PCBs may be about five percent.The trace impedance variation between a first location on a first layerand a second location on a second layer (microstrip) is approximatelyseven to ten percent.

[0011] While impedance compensation circuitry facilitates impedancematching, it fails to consider the differences in trace impedancesbetween same-layer and different-layer traces. Thus, there is a need todevelop impedance compensation circuitry that accounts for the knownvariations in trace impedances.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]FIG. 1 is a block diagram of a system employing impedancecompensation according to the prior art;

[0013]FIG. 2 is a schematic diagram of a four-layer printed circuitboard according to the prior art; and

[0014]FIG. 3 is a block diagram of a system employing impedancecompensation according to the described embodiments of the invention.

DETAILED DESCRIPTION

[0015] According to the embodiments described herein, a system andmethod are disclosed in which separate impedance compensation circuitryis allocated for an interface according to the space occupied on aprinted circuit board (PCB) by the interface. Where an interfaceoccupies two or more layers of the PCB, an impedance compensationcircuit is dedicated to each layer on behalf of the interface. Bydedicating impedance compensation, not just to the interface alone, butto the physical space occupied by the interface, the system and methodare able to exploit same layer trace impedances, save board space and/orprovide AC timings recovery.

[0016] In the following detailed description, reference is made to theaccompanying drawings, which show by way of illustration specificembodiments in which the invention may be practiced. However, it is tobe understood that other embodiments will become apparent to those ofordinary skill in the art upon reading this disclosure. For simplicity,a four-layer printed circuit board is used in the described embodiments.However a system employing any multilayer PCB can utilize the principlesof the claimed invention. Further, although a small number of systeminterfaces are described, any interface employing impedance compensationcan utilize the principles of the claimed invention. The followingdetailed description is, therefore, not to be construed in a limitingsense, as the scope of the present invention is defined by the claims.

[0017] In FIG. 1, according to the prior art, a system 50 includes amemory interface 22, an input/output (I/O) interface 24, and a processorinterface 26. These interfaces may be part of a processor-based system,such as a computer, a personal digital assistant (PDA), a cellulartelephone, or other electronic device. The system 50 may include otherinterfaces not shown.

[0018] Also depicted in FIG. 1, impedance compensation circuits 22A,22B, and 22C (collectively, impedance compensation circuits 22), areconnected to the memory interface 22, the I/O interface 24, and theprocessor interface 26, respectively. A separate impedance compensationcircuit 22 is thus allocated for each interface in the system 50. Eachimpedance compensation circuit 22 ensures that the impedance of itsassociated interface matches, as closely as possible, the impedances ofsignal traces coupled to the interface.

[0019] The various interfaces of the system 50 are distributed upon oneor more layers of a PCB 10. In FIG. 1, the PCB 10 is a four-layer board,comprising two signal layers 22A and 22B (collectively, signal layers22), a power layer 14, and a ground layer 16. For simplicity, afour-layer PCB is depicted, but the system 50 can populate anymulti-layered PCBs comprising at least two signal layers.

[0020] Each interface comprises two portions, one to populate eachsignal layer of the PCB 10. Dotted lines denote the physical location ofeach portion. Memory interface 22A occupies signal layer 12A and memoryinterface 22B occupies signal layer 12B. Likewise, I/O interface 24Aoccupies signal layer 12A and I/O interface 24B occupies signal layer12B.

[0021] PCBs are manufactured according to certain specifications,including the impedance of the traces on the PCB. One or more traceimpedances are specified to the PCB manufacturers, who then deliver theboards that meet the specified impedances within a range. Some personalcomputer motherboards are designed with 50- and 60-ohm traces, as oneexample. Multiple trace impedances allow interfaces with distinctimpedance requirements to occupy the same PCB. Thus, for example, in thesystem 50 of FIG. 1, the 50-ohm traces may be used by the processorinterface 26 while the 60-ohm traces are used by the memory interface22.

[0022] Further, these trace impedances are designed to be within acertain range, known as its tolerance. Personal computer motherboards,for example, typically have a tolerance of +/−15%. The design of thesystem is expected to account for the tolerance. Thus, for example, thememory interface 22 is designed to expect trace impedances to beanywhere from 51 to 69 ohms.

[0023] However, as the dotted lines in FIG. 1 illustrate, each interfaceof the system 50 may physically occupy more than one signal layer of thePCB 10. The impedance compensation circuit 20A measures the traceimpedance at a single trace located on the signal layer 12A, thencalibrates the I/O buffers for the memory interface 22A (on the signallayer 12A) and for the memory interface 22B (on the signal layer 12B).

[0024] This phenomenon is illustrated in the schematic diagram of thePCB 10 in FIG. 2. The PCB 10 includes signal layers 12A and 12B, as wellas power layer 14 and ground layer 16. Signal traces 32A, 32B, and 32C(collectively, signal traces 32) are featured, in which signal traces32A and 32B are on signal layer 12A while signal trace 32C is on signallayer 12B. Each signal trace 32 has an associated trace impedance ofsome value, expressed in ohms. Thus, signal trace 32A has a traceimpedance X, signal trace 32B has a trace impedance Y, and signal trace32C has a trace impedance Z. Assuming the PCB 10 has a tolerance of+/−15%, the values X, Y, and Z are expected to be within +/−15% of oneanother.

[0025] Studies have shown that the variation of measured traceimpedances on a single layer is lower than when trace impedances ondistinct layers are measured. Thus, for example, where the traceimpedances of traces 32A and 32B are compared, the difference istypically smaller than when the trace impedances of traces 32A and 32Care compared. Empirically, same layer variation between trace impedancesis measured at approximately five percent, according to one embodiment.Thus, if trace 32A has a trace impedance of 50 ohms, the trace impedanceof trace 32B is expected to be within five percent of 50 ohms, orbetween 47.5 ohms and 52.5 ohms.

[0026] Empirical measurements of traces between two different signallayers (where one of the layers is a microstrip, or outside layer) isnoticeably different than same layer measurements, according to oneembodiment. In this case, a variation of between seven and ten percentis observed. Thus, if trace 32A has a trace impedance of 50 ohms, thetrace impedance of trace 32C may be as much as ten percent greater thanor less than 50 ohms, or between 45 and 55 ohms.

[0027] When the percentage difference between a first trace impedance ona first layer and a second trace impedance on a second layer is lowerthan the manufacturer-specified tolerance, an improved, or tighter,multi-layer impedance tolerance is available. Likewise, when thepercentage difference between a first trace impedance and a second traceimpedance on a single layer is lower than a manufacturer-specifiedtolerance, an improved, or tighter, single layer impedance tolerance isavailable. The improved single-layer and multi-layer tolerances areexploited by the system 100, as shown in FIG. 3.

[0028] As in FIGS. 1 and 2, the four-layer PCB 10 features signal layers12A and 12B, as well as power 14 and ground 16. The system 100 alsoincludes a memory interface 22, an I/O interface 24, and a processorinterface 26. A separate impedance compensation circuit is dedicated toeach layer of the PCB 10 for each interface supported. As in FIG. 1,each interface is separated into two distinct blocks, one for eachsignal layer occupied by the interface.

[0029] Thus, memory interface 22A, which populates signal layer 12A, isconnected to its own impedance compensation circuit 40A. Memoryinterface 22B, residing on signal layer 12B, is connected to impedancecompensation circuit 40B. Likewise, I/O interface 24A (on signal layer12A) is connected to impedance compensation circuit 40C while I/Ointerface 24B (on signal layer 12B) is connected to impedancecompensation circuit 40D. Processor interface 26A (on signal layer 12A)is connected to impedance compensation circuit 40E while processorinterface 26B (on signal layer 12B) is connected to its own impedancecompensation circuit 40F.

[0030] By using impedance compensation circuitry for each signal layerof the PCB, interface signals laid out on a specific layer can estimatea lower variation of trace impedance in the design. Even though theboard is still manufactured to meet a certain impedance requirement plustolerance, the board design can depend on the same layer improvedimpedance tolerance to influence the design. Issues such as how farapart the traces can be, the length and width of the traces used by theinterface, the PCB board size, the number of ICs to populate the PCBboard space, and so on, are easier to make when a smaller tolerance inthe board impedance is expected. Despite the presence of more impedancecompensation circuits, improved board routing space is found, in someembodiments.

[0031] The principle of associating an impedance compensation circuitwith each portion of an interface that occupies a distinct PCB layer canbe extended to other multiple-layer PCB board designs. For example,where the interface occupies three layers, three impedance compensationcircuits can be used, one dedicated to each portion of the interface oneach layer. This can extend to any number of signal layers.

[0032] In other embodiments, the AC timings recovery can be improved, inwhich the speed of signals used in the system 100 increases. In additionto or instead of improving the board routing space, the design of thesystem can be modified to accept signals of higher frequencies. Higherfrequency signals typically are more sensitive to impedance changes. Thelower tolerance of trace impedances in the system 100, as compared tothe system 50, can permit the use of higher frequency signals.

[0033] While the invention has been described with respect to a limitednumber of embodiments, those skilled in the art will appreciate numerousmodifications and variations therefrom. It is intended that the appendedclaims cover all such modifications and variations as fall within thetrue spirit and scope of the invention.

We claim:
 1. A system comprising: an interface comprising a firstportion and a second portion, where the first portion populates a firstlayer of a printed circuit board and the second portion populates asecond layer of the printed circuit board, wherein signals aretransmitted between the first portion and the second portion; and animpedance compensation circuit residing on the first layer of theprinted circuit board and coupled to the first portion of the interface,wherein the first impedance compensation circuit controls the impedanceof signals associated with the first portion of the interface but doesnot control the impedance of signals associated with the second portionof the interface.
 2. The system of claim 1, further comprising: a secondimpedance compensation circuit residing on the second layer of theprinted circuit board and coupled to the second portion of theinterface, wherein the second impedance compensation circuit controlsthe impedance of signals associated with the second portion of theinterface.
 3. The system of claim 2, further comprising: a thirdimpedance compensation circuit residing on a third layer of the printedcircuit board, wherein the interface comprises a third portionpopulating the third layer, wherein the third impedance compensationcircuit controls the impedance of signals associated with the thirdportion of the interface.
 4. A method comprising: identifying aninterface of a system, the interface comprising a first portion and asecond portion, wherein the first portion populates a first layer of aprinted circuit board and the second portion populates a second layer ofthe printed circuit board; and associating a first impedancecompensation circuit with the first portion, wherein the first impedancecompensation circuit controls the impedance of signals pertaining to thefirst portion of the interface but does not control the impedance ofsignals pertaining to the second portion of the interface.
 5. The methodof claim 4, further comprising: associating a second impedancecompensation circuit with the second portion, wherein the secondimpedance compensation controls the impedance of signals pertaining tothe second portion of the interface.
 6. The method of claim 5, furthercomprising: specifying a number of integrated circuits to populate thefirst layer of the printed circuit board, the number being based on amanufacturer-specified tolerance of the printed circuit board;identifying an improved multi-layer impedance tolerance relative to amanufacturer-specified tolerance; and increasing a number of integratedcircuits on the printed circuit board.
 7. The method of claim 5, furthercomprising: specifying a number of integrated circuits to populate thefirst layer of the printed circuit board, the number being based on amanufacturer-specified tolerance of the printed circuit board;identifying an improved single-layer impedance tolerance relative to amanufacturer-specified tolerance; and increasing a number of integratedcircuits on the printed circuit board.
 8. The method of claim 5, furthercomprising: specifying a width for one or more traces on the first layerof the printed circuit board; identifying an improved multi-layerimpedance tolerance relative to a manufacturer-specified tolerance; anddecreasing the width for the one or more traces on the printed circuitboard.
 9. The method of claim 5, further comprising: specifying a widthfor one or more traces on the first layer of the printed circuit board;identifying an improved single-layer impedance tolerance relative to amanufacturer-specified tolerance; and decreasing the width for the oneor more traces on the printed circuit board.
 10. The method of claim 5,further comprising: specifying a width between traces for one or moretraces on the first layer of the printed circuit board; identifying animproved multi-layer impedance tolerance relative to amanufacturer-specified tolerance; and decreasing the width betweentraces of two or more traces on the printed circuit board.
 11. Themethod of claim 5, further comprising: specifying a width between tracesfor one or more traces on the first layer of the printed circuit board;identifying an improved single-layer impedance tolerance relative to amanufacturer-specified tolerance; and decreasing the width betweentraces of two or more traces on the printed circuit board.
 12. Themethod of claim 5, further comprising: specifying a speed of one or moresignals to operate within the system; identifying an improvedmulti-layer impedance tolerance relative to a manufacturer-specifiedtolerance; and increasing the speed of one or more signals on theprinted circuit board.
 13. The method of claim 5, further comprising:specifying a speed of one or more signals to operate within the system;identifying an improved single-layer impedance tolerance relative to amanufacturer-specified tolerance; and increasing the speed of one ormore signals on the printed circuit board.
 14. The method of claim 5,further comprising: specifying a size of the printed circuit board, thesize being based on a manufacturer-specified tolerance of the printedcircuit board and a number of integrated circuits comprising theinterface; identifying an improved multi-layer impedance tolerancerelative to a manufacturer-specified tolerance; and decreasing the sizeof the printed circuit board.
 15. The method of claim 5, furthercomprising: specifying a size of the printed circuit board, the sizebeing based on a manufacturer-specified tolerance of the printed circuitboard and a number of integrated circuits comprising the interface;identifying an improved single-layer impedance tolerance relative to amanufacturer-specified tolerance; and decreasing the size of the printedcircuit board.
 16. The method of claim 5, further comprising: specifyingone or more interconnect lengths between traces on the printed circuitboard; identifying an improved multi-layer impedance tolerance relativeto a manufacturer-specified tolerance; and extending the interconnectlengths between traces on the printed circuit board.
 17. The method ofclaim 5, further comprising: specifying one or more interconnect lengthsbetween traces on the printed circuit board; identifying an improvedsingle-layer impedance tolerance relative to a manufacturer-specifiedtolerance; and extending the interconnect lengths between traces on theprinted circuit board.